Fast program to program verify method

ABSTRACT

In the present invention a new method for program and program verify is described. The threshold voltage of the memory cell is shifted up and then measured with minimal charging and discharging of the bit lines and control gate lines. Bit line to control gate line capacitance is also used to reduce the number of voltage references needed. Program current is reduced by use of a load device coupled to the source diffusion. The result is increased program bandwidth with lower high voltage charge pump current consumption.

[0001] This application claims priority to Provisional PatentApplication serial No. 60/255,824, filed on Dec. 15, 2000, which isherein incorporated by reference.

BACKGROUND OF THE INVENTION

[0002] 1. Field of Invention

[0003] The present invention is related to semiconductor nonvolatilememory and in particular to program and program verify for twin MONOSflash memories.

[0004] 2. Description of related art

[0005] In MONOS flash memory devices, data is stored as electrons in thenitride region of an oxide-nitride-oxide (ONO) composite layer under acontrol gate. The presence of electrons in the nitride region increasesthe threshold of the device. An erased cell with a logical “1” storedhas few or no stored electrons in the nitride region, and a programmedcell with a logical “0” stored has a fixed range of electrons in thenitride region. In conventional MONOS memories, the program operation isinterrupted by program verify cycles in order to control the number ofelectrons in the nitride region. A state diagram of prior art for aprogram operation with program verify is shown in FIG. 1. In the firstprogram setup 101 is needed to startup the charge pumps and setup thevoltages needed for the program operation. The selected memory cell issubjected to program voltage conditions during the program pulse step102. After a fixed time, the threshold of the memory cell is tested inthe program verify step 103. If the threshold of the memory cell isgreater than the reference threshold, then the memory cell is deemed tohave been programmed, and program is complete 104. Otherwise if thethreshold of the selected memory cell is not high enough, then thememory cell is placed back into the program state 102.

[0006]FIG. 2a gives an example of voltage conditions of a MONOS memorycell of prior art for program and for program verify of prior art inFIG. 2b. The memory cell is composed of a control gate 202, a source 201and a drain 203. Electrons are stored in the nitride region 204 underthe control gate 202. It should be noted that the voltages that areshown are an example only. Actual voltages depend on many specificationssuch as program speed, oxide thickness, and memory cell dimensions. ForCHE (channel hot electron) injection program, a voltage of approximately10V is applied to the control gate 202 and another high voltage ofapproximately 5V is applied to the drain 203 with the source 201grounded.

[0007] Referring to FIG. 2b, program verify is very similar to a readoperation, in that one diffusion will be measured with respect to areference to determine the memory state. The control gate 202 is biasedto approximately 2V, the drain 201 is biased to approximately 1V and thesource 203 is biased to 0V. Whenever there is a transition betweenprogram and program verify states, it is necessary to swap the sourceand drains and to lower the drain 203 voltage from 5V to 0V. If anotherprogram cycle is necessary, the drain 203 is raised to 5V again. This isan inefficient usage of charge, because extra current is needed to raiseand lower the drain voltage between program and program verify cycles.When the drains of many memory cells are connected to a single highlycapacitive bit line, the transition time between program and programverify increases. This increased transition time increases the overallprogram operation time.

[0008]FIG. 3 shows a prior art dual storage MONOS memory device (calledNROM) in which there are two memory storage sites 304 and 305 within onememory cell, described in U.S. Pat. No. 6,011,725 (Eitan), which isdirected to a method of read described called “reverse read”. Thediffusion 303, which is closest to the selected memory storage region305, becomes the lower voltage or source whereas the diffusion 301,which is opposite the selected memory storage region 305, becomes thehigher voltage or drain. The drain voltage is higher than the sourcevoltage in order to create a depletion region into the substrate andthus “override” the charge that may be stored in the unselected memorystorage region, if it is in the high threshold “0” memory state. Thistype of NROM memory cell can only operate in reverse read mode, becausea higher voltage is needed on the unselected memory storage side tooverride the unselected memory channel. If the device were to be read inthe forward direction, then the higher drain voltage would override theselected memory storage side, and the cell would always be sensed to bein a low Vt “1” memory state.

[0009] Another prior art dual storage MONOS device is described inpatent application Ser. No. 09/426,692, filed Oct. 25, 1999, called thetwin MONOS cell and shown in FIG. 4a. In this type of memory cell thereare two extra side wall polysilicon control gate structures 406 and 407in addition to the word gate 402 and two diffusions 401 and 403. Unlikethe control gate 302 of FIG. 3, the word gate 402 of FIG. 4a does nothave memory nitride storage regions underneath itself. Instead, thememory storage regions lie underneath the side wall polysilicon controlgates 406 and 407. As shown in FIG. 4a, two side wall polysilicon gatesbetween two adjacent memory cells are electrically connected together todefine one equivalent control gate. Because the additional control gates406 and 407 provide another level of flexibility, the twin MONOS cellcan be easily read in both the reverse and forward directions. Thechannel underneath of the unselected nitride storage site can beoverridden by increasing the voltage of the associated control gate to avoltage which is some delta above the highest possible threshold voltage(Vcg override). Although the twin MONOS cell is able to read in bothdirections, the forward read has slower read performance, due to lowercell current, smaller threshold margins, and limited voltage range. FIG.4b shows the relationship of drain voltage v.s. the threshold of theselected nitride region for memory nitride channel lengths of >50 nm and<50 nm. It can be seen that during forward read, the high Vt cell (“0”)suffers degradation of threshold at higher drain-source voltages. Thiseffect becomes more severe for shorter channel lengths. Thus it isdesirable to keep the drain voltage to lower than approximately 0.3-0.5Vduring sensing in order to maintain reasonable threshold margin betweenthe “1” and “0” cell.

[0010]FIG. 4c is a schematic representation of the twin MONOS cell arrayin the diffusion bit configuration. Each memory cell consists of oneword gate, two control gate halves, under which each control gate halfis one nitride storage region, and two diffusion halves. In this array,memory cells are arranged in rows and columns, in which word gates arehorizontally connected together by word lines WL[0-1], and bitdiffusions are vertically connected together by bit lines BL[0-3], andcontrol gates are vertically connected together by control linesCG[0-3]. Control lines CG[0-3] and bit lines BL[0-3] may run atop of oneanother and have a coupling capacitance of about 30%.

[0011] For high bandwidth program applications, it is desirable toprogram many memory cells in parallel. If many bit lines and controllines are need to be charged and discharged between program and programverify cycles, the voltage and current requirements of the charge pumpsand voltage regulators will be very high, which impacts power andoverall program time. In multi-level storage memories especially, thenumber of program and program verify cycles is greater in order to havetighter control between threshold states. Thus it is desirable tominimize the voltage transitions between program and program verify.

SUMMARY OF THE INVENTION

[0012] It is an objective of the present invention to provide a lowpower method of programming a dual storage site MONOS memory cell.

[0013] It is also an objective of the present invention to provide amethod of program verify for a dual storage site MONOS memory cell.

[0014] It is still an objective of the present invention to efficientlyswitch between program and program verify operations.

[0015] It is another objective of the present invention to minimizetransition between program and program verify by minimizing the chargingand discharging the diffusion bit line.

[0016] It is another objective of the present invention to minimizetransition between program and program verify by minimizing the chargingand discharging of control gate voltages.

[0017] It is another objective of the present invention to minimize thenumber of reference voltages required for program and program verify.

[0018] It is also another objective of the present invention to useforward read for program verify.

[0019] It is also another objective of the present invention to usereverse read for program verify.

[0020] It is another objective of the present invention to usecapacitive coupling between the control gate line and the bit line inorder to achieve a target threshold voltage by minimal voltageapplication to the control lines and bit lines.

[0021] It is another objective of the present invention to protect theadjacent cell from program disturb.

[0022] It is still another objective of the present invention to controlprogram cell current by connecting a load transistor to the sourcediffusion.

[0023] It is yet an objective of the present invention to maintaincontrol gate voltages for program and program verify to be the same.

[0024] In the present invention a method to produce a fast switchbetween program and program verify is described for a MONOS memorydevice. The word gate of the cell to be programmed is biased to a lowvoltage to limit memory cell current to a few microamperes. The draindiffusion is biased to a high voltage and the source diffusion isgrounded. The drain diffusion is the diffusion near the storage site tobe programmed in a two storage site device. The storage site is anitride region located below a control gate. In a two storage sitedevice there are two control gates and two separate nitride regions. Theunselected control gate is biased to a high voltage to override thehighest possible threshold voltage of the memory storage region beneaththe unselected control gate. The selected control gate is the controlgate above the storage site to be programmed and is biased to a highvoltage for electron injection into the nitride storage site. The sourcediffusion can be connected to a load device to limit and control cellcurrent, and cell current can be controlled with a low word gatevoltage. To control program disturb of the adjacent cell, the voltage ofthe unselected diffusion of the adjacent cell is increased slightly.Increasing the voltage of the unselected adjacent diffusion decreasesthe gate to source voltage as well as increases the threshold voltage ofthe adjacent storage region and protects the cell from program disturb.

[0025] In order to program a memory cell of the present invention aprogram verify operation is necessary to determine if the cell beingprogrammed has reach a sufficient program voltage. To do this there is aminimum of one switch from the program operation to a program verifyoperation and back. There can be several switches between operationsduring the programming of a cell. If the voltages involved in the twooperations are substantially dissimilar, there is considerable chargingand discharging of the various connecting lines, which results in timedelays. To minimize the time delays between the two operations the bitline voltages and the control gate voltages are made the same as much aspossible during both program and program verify. Also one variation ofprogram verify uses a “forward read” direction which puts the lowervoltage on the diffusion opposite the selected nitride storage site. The“forward read” operation allows minimal charging and discharging of thebit lines and control gates. This forward read approach is mosteffective when the channel length under the nitride region is long andthe threshold voltage reduction as a function of drain-source voltage,shown in FIG. 4b, is small.

[0026] In order to program verify a selected nitride region in a twinMONOS memory cell, the source and drain bit lines are equalized to avoltage that is half of the high drain voltage during program. At thesame time, the selected control gate voltage is lowered slightly, andthe word line is then raised to a higher voltage to allow the word gatechannel to conduct. Finally, one of the two bit lines is pulled down toa lower voltage. A sense amplifier connected to the bit line monitorsthe other bit line with respect to a reference voltage; if the targetnitride region has been programmed enough, the voltage will bemaintained, otherwise it will also fall. Verify can be performed in boththe forward and reverse directions by choosing which of the two bitlines to pull down, or connect to the sense amplifier.

[0027] Another program method is described in which program is performedby utilizing the capacitance of the BL. Due to the high injectionefficiency of the channel hot electron (CHE) program for the twin MONOSmemory, program can be sufficiently completed within a short time, byusing the charge stored on the capacitance of the high voltage drainside bit line. Program verify is performed by utilizing capacitance ofthe BL and the coupling capacitance between the bit lines and thecontrol gate lines in order to increase the threshold voltage range.First the appropriate voltages are applied to the control gate lines andbit lines for the program. The control gate lines and bit lines are thenfloated and the word line is raised to a low voltage to limit theprogram current. When the word line turns on, all channels between thesource and drain are on, so that charge will flow between the two bitlines. However, the low voltage of the word line also limits the sourcebit line voltage. When the drain side bit line voltage falls past acertain point, injection will stop. In order to program verify, the wordline is raised to a high voltage in order for both bit lines to equalizeto a middle voltage. Thereafter, the bit line closest to the selectednitride region will be pulled down to a lower voltage. The threshold ofthe verify operation is determined by the control gate voltage of theselected side minus the lower bit line voltage. The voltage of theopposite bit line may be monitored to determine whether the selectednitride region has been programmed enough such that the bit line voltageis maintained, and doesn't fall.

[0028] The program to program verify sequences described in the presentinvention may also be applied to high program bandwidth applications forstorage of multiple threshold levels in a single nitride region.

BRIEF DESCRIPTION OF THE DRAWINGS

[0029] This invention will be described with reference to theaccompanying drawings, wherein:

[0030]FIG. 1 is a method of prior art used to program and program verifya nonvolatile memory cell;

[0031]FIG. 2a is a diagram of a MONOS cell of prior art showing voltagesfor program;

[0032]FIG. 2b is a diagram of a MONOS cell of prior art showing voltagesfor program verification;

[0033]FIG. 3 is a diagram of a dual storage MONOS cell of prior art;

[0034]FIG. 4a is a diagram of a dual storage MONOS cell of prior artwith dual control gates;

[0035]FIG. 4b is a graph showing the relationship between thresholdvoltage and drain-source voltage of a dual storage MONOS cell of priorart with dual control gates;

[0036]FIG. 4c is a schematic of an array of dual storage MONOS cells ofprior art with dual control gates.

[0037]FIG. 5a is a diagram of a dual storage MONOS cell of the presentinvention showing voltages for a program operation of the firstembodiment;

[0038]FIGS. 5b-d are diagrams of a dual storage MONOS cell of thepresent invention showing voltages for a program verify operation of thefirst embodiment;

[0039]FIG. 6 is a diagram of simulation results for the program andprogram verify method of the first embodiment;

[0040]FIG. 7 is a diagram of a dual storage MONOS cell of the presentinvention showing voltages for a program verify operation of the secondembodiment;

[0041]FIGS. 8a-b are diagrams of a dual storage MONOS cell of thepresent invention showing voltages for a program operation of the thirdembodiment;

[0042]FIGS. 8c-d are diagrams of a dual storage MONOS cell of thepresent invention showing voltages for a program verify operation of thethird embodiment;

[0043]FIG. 9 is a diagram of simulation results for the program andprogram verify method of the third embodiment; and

[0044]FIG. 10 is a diagram of two adjacent dual storage MONOS cells ofthe present invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT

[0045] Based on the memory cell structure in FIG. 4a, program and verifyconditions for the twin MONOS memory cell of patent application Ser. No.09/426,692, filed Oct. 25, 1999, are given in FIG. 5a through FIG. 5d.The memory cell 410 is comprised of one word gate 402, a left diffusionregion 401, a right diffusion region 403, and two control gates 406 and407, and two nitride storage sites 404 and 405. The left nitride storagesite 404 is positioned under the left control gate 406, above the leftdiffusion 401, and close to the word gate 402. The right nitride storagesite 405 is positioned under the right control gate 407, above the rightdiffusion 403, and close to the word gate 402.

[0046] It should be noted that the program condition shown aresignificantly lower than the program voltages for a conventional MONOSdevice. The voltage difference is due to the enhanced electron injectionmechanism for the twin MONOS device. However, it should also be notedthat the voltages shown are approximations only. The actual voltagesneed to be determined based on process and product specification factorssuch as threshold shift, oxide and ONO thickness, doping profiles, andthe program and erase time specifications. It is assumed that thethreshold for a “0” state is Vth>2.0V, the threshold for a “1” state isabout 0.5V, and the word gate 503 threshold is 0.5V.

[0047] Based on the memory cross section of FIG. 4a, FIG. 5a shows thevoltage conditions of the present invention, when the right nitridestorage site is selected. In order to program to the right nitridestorage site 405, an approximate 5V drain to source voltage is appliedacross the memory cell. For CHE injection, the diffusion 403 closest tothe selected storage site becomes the drain. Of the two diffusionregions 401 and 403, the right diffusion 403 is determined have the highdrain voltage of about 5V, and the left diffusion 401 becomes thesource, which is around 0V. A low word gate voltage of approximately 1Vlimits program cell current. The left control gate 406 is biased to ahigh voltage of approximately 5V to override a possible high thresholdstate in the unselected memory storage region 404. Although a programoperation is still possible for a lower left control gate voltage ofaround 3V if the target program threshold is about 2.0V, the highervoltage of 5V is selected to be the same override voltage as used duringprogram verify to reduce the transition time between program and programverify modes. The right control gate 407 is biased to 5V.

[0048]FIG. 5b gives the voltage conditions during transition betweenprogram and program verify mode. When switching between program andprogram verify mode, the high control gate voltages do not need to bedischarged down to the low voltages for a normal read operation, whichsaves charge pump current and mode switching time. Instead, the controlgate 406 remains near 5V. The source diffusion 401 and drain diffusion403 is equalized to about 2.5V, which is half of the high drain voltageused for program. At the same time, the voltage of the right controlgate 407 is changed to Vcg_pv, which is about 4V for a target thresholdof 2.0V, when body effect is considered. After the voltages of both theleft and right diffusion 401 and 403 have settled to 2.5, bothdiffusions are floated as shown in FIG. 5c. The word gate 402 is thenraised to a high voltage of about 4V, in order to allow the diffusionvoltages of 2.5V to pass easily. It is also possible to equalize the bitlines at the same time the word line is being raised. The final step ofthe program verify sequence is shown in FIG. 5d. The voltage of theright diffusion 403 is pulled down to Vbl_pv, which can be about 1.8Vand the voltage of the left diffusion 401 is monitored. If the thresholdof the right nitride region 405 is greater than the target 2.0V, thenthe left diffusion 401 voltage will remain at about 2.5V. Otherwise, ifthe threshold is lower than 2.0V, the left diffusion 401 voltage willfall. Because the lower of the two diffusion voltages is on the sameside as the selected nitride region, the read direction is reverse read.The target program threshold voltage is determined by the voltage ofVcg_pv and the Vbl_pv, where Vtarget_threshold≈Vcg_pv−Vbl_pv,considering that the nonzero source-substrate voltage introduces a bodyeffect component to Vtarget_threshold.

[0049]FIG. 6 shows simulation results for the program verify sequencedescribed by FIGS. 5a through d for the first embodiment. Shown arevoltage curves versus time for the left control gate CGL 406, the rightcontrol gate CGR 407, the word gate WL 402, the left bit line BLL 401,and the right bit line BLR 403. The effects of threshold voltage areshown for the left bit line BLL 401.

[0050] In a second embodiment of the present invention, program verifycan be conducted in the forward read direction. The program and verifysequences shown in FIGS. 5a through c are the same. However, in the laststep, the voltage conditions in FIG. 7 are substituted for those of FIG.5d. In forward read, the source and drain diffusions swap compared toduring reverse read. The voltage of the left diffusion 401 farther fromthe selected nitride 405 is pulled down to a voltage of Vbl_pv. Thevoltage of the right diffusion 403 closer to the selected nitride region405 is monitored to determine the threshold value. If the selectednitride region 405 threshold is greater than 2.0V, then the rightdiffusion voltage 403 will be maintained. For forward read, thresholdvoltage degrades as a function of drain-source voltage, so it isimportant to keep the drain to source voltage to between 0.3 to 0.5V. Inorder to verify a target threshold of 2.0V, Vcg_pv should be 2.0V (plussome additional voltage to account for body effect) greater than theVbl_pv.

[0051] In a third embodiment of the present invention, the sequence forprogram is given in FIGS. 8a through b, and the program verify sequenceis shown in FIGS. 8c through d.

[0052]FIG. 8a gives the voltage conditions in order to program the rightnitride region 405 of the twin MONOS memory cell of FIG. 4a. The leftcontrol gate 406 is biased to an override voltage of about 5V. The rightcontrol gate 407 is biased to a selected program voltage ofapproximately 5V. The left diffusion 401 is grounded and the rightdiffusion 403 is raised to a high drain voltage of approximately 5V.After the bit lines and control gate lines which are connected to therespective diffusions 401 and 403, and control gates 406 and 407 of theselected memory cell have settled to their proper voltages, they aredisconnected from their voltage supplies and are floated. The word line,which is connected to word gate 402, is then raised and program beginswhen electrons start to flow from the source bit line to the drain bitline. The high CHE injection efficiency of the twin MONOS cell of thepresent invention allows sufficient programming using the energy storedin the high drain voltage bit line, without actually DC biasing of thesource and drain. The word line voltage also limits the extent of bitline equalization, because the source bit line will not rise past thevoltage of the word line minus the threshold voltage of the word gate,which is approximately 0.5V. Thus, after the source bit line rises to0.5V, and the drain bit line falls to 4.5V, charge will no longer flowbetween the two bit lines and so CHE injection will stop. Changes in thebit line voltages also affect the voltages of the two floating controlgate lines. If we assume that the bit line to control gate line couplingratio is about 30%, then a 0.5V bit line voltage change will result in a0.15*0.3=0.15V control gate line voltage change. The bit line andcontrol gate voltages after program has stopped are given in FIG. 8b.

[0053] In FIG. 8c, the word gate 402 voltage is raised to a highervoltage of about 4V in order to equalize the left and right bit lines toa middle voltage of approximately 2.5V and then floated. At the sametime that the bit lines converge to 2.5V, the control gate voltages,which are capacitive coupled, such that the left control gate 406 risesto 5.75V and the right control gate 407 falls to 4.25V. This voltage ofthe right control gate 407 is equivalent to the Vcg_pv in the firstembodiment of the present invention.

[0054] As shown in FIG. 8d, when the voltage of the right side diffusion403 is pulled down to Vbl_pv, it is then possible to determine if thethreshold of the selected nitride region is greater than the targetthreshold voltage Vtarget_threshold (whereVtarget_threshold≈Vcg_pv−Vbl_pv), by monitoring the bit line connectedto the left diffusion 404. If the voltage is maintained, or remainshigher with respect to a given voltage, then programming is sufficient,otherwise the voltage of the left diffusion 404 will fall.

[0055] The advantage of the third embodiment over the first embodimentis that Vcg_pv does not have to be externally applied to the memorycell. Instead, it can be derived by a unique timing sequence andutilizing the capacitive coupling between the bit line and control gateline.

[0056]FIG. 9 shows simulation results for the program verify sequencedescribed by FIGS. 8a through d for the third embodiment. Shown arevoltage curves versus time for the left control gate CGL 406, the rightcontrol gate CGR 407, the word gate WL 402, the left bit line BLL 401,and the right bit line BLR 403. The effects of threshold voltage areshown for the left bit line BLL 401 and the left control gate 406.

[0057] The first and third embodiments of the present invention may beapplied to high program bandwidth applications for storage of multiplethreshold levels in a single nitride region. By applying the formulaVtarget_threshold≈Vcg_pv−Vbl_pv, the desired threshold can be tightlycontrolled. (Note: body effect due to source-substrate bias needs alsoneeds to be considered) Based on the simulation data of FIG. 6 and FIG.9, threshold voltage increments of less than 0.1V can be resolved bysetting the values of Vcg_pv or Vbl_pv, or both.

[0058] In the first, second and third embodiments, during the programverify sequence, it is also possible to equalize the bit lines usinganother transistor, which can be connected between the left and rightbit lines. The gate of this transistor could be activated during theequalization phase and deactivated at all other times.

[0059] In the first, second, and third embodiments, program verify timecan be reduced by setting Vcg_pv−Vbl_pv>Vtarget_threshold. Both theinsufficiently programmed bit line and the sufficiently programmed bitline voltages will fall, however it is possible to distinguish betweenthe two cases by comparing the bit line voltage to a reference voltageor reference cell. If the bit line fall remains above the referencevoltage within a given time interval, then the cell has been programmedenough.

[0060] In another embodiment of the present invention, during program,the adjacent cell is protected from program disturb by raising slightlythe voltage of the opposite diffusion. FIG. 10 shows a cross-section oftwo adjacent memory cells 601 and 602. When the right selected memorystorage region 608 of the left cell 601 is to be to be programmed, theadjacent memory storage region 609 in the adjacent cell 602, sharing thesame high voltage control gate and high voltage diffusion 605, is indanger of program disturb. If the opposite right side memory storageregion 610 in the right cell 602 has a negative threshold, it ispossible that the adjacent right cell 602 may conduct current, therebyprogramming the memory storage region 609 of the unselected adjacentcell. In order to protect unselected adjacent memory cell storage region609 from program disturb, the unselected adjacent diffusion 606 isbiased to a slightly high voltage, approximately 1V. Increasing thevoltage of the unselected adjacent diffusion 606 effectively increasesthe threshold of the memory storage region 610, as well as raises thesource voltage of the cell. It is important that this diffusion voltagenot be too high, or program disturb may propagate to the adjacent cellof the adjacent cell of 601. In another embodiment of the presentinvention, during program, the current of the memory cell is controlledby connecting a current load transistor to the left source diffusion401.

[0061] While the invention has been particularly shown and describedwith reference to preferred embodiments thereof, it will be understoodby those skilled in the art that various changes in form and details maybe made without departing from the spirit and scope of the invention.

What is claimed is:
 1. A method of programming a dual storage site MONOSmemory cell, comprising: a) biasing a drain diffusion to a first highvoltage, b) biasing a source diffusion to ground, c) biasing aunselected control gate to a second high voltage, d) biasing a selectedcontrol gate to a third high voltage, e) biasing a word gate to a lowvoltage,
 2. The method of claim 1, wherein said source diffusion isconnected to a load device to limit current.
 3. The method of claim 1,wherein biasing said word gate to a low voltage limits memory cellcurrent.
 4. The method of claim 3, wherein biasing said word gate to alow voltage limits memory cell current to less than a few microamperes.5. The method of claim 1, wherein biasing said unselected control gateto a second high voltage overrides a highest possible threshold of amemory storage region that is beneath said unselected control gate. 6.The method of claim 1, wherein biasing said selected control gate tosaid third high voltage facilitates electron injection into a memorystorage region beneath said selected control gate.
 7. The method ofclaim 1, wherein biasing said drain diffusion with said first highvoltage and said selected control gate with said third high voltagecreates a condition for disturb of an adjacent cell that is suppressedby increasing a voltage on an unselected diffusion of said adjacentcell.
 8. A method to program verify a dual storage site MONOS memorycell using a reverse read operation, comprising: a) maintaining a firstvoltage coupled to a first control gate located above an unselectedstorage site of a MONOS memory cell to be same as for a programoperation, b) lowering a second voltage coupled to a second control gateabove a selected storage site of said memory cell to a value less thanthat used for said program operation, c) disconnecting and floating adrain diffusion and a source diffusion of said memory cell, then d)equalizing said drain diffusion voltage and said source diffusionvoltage of said memory cell, e) biasing a word gate voltage of saidmemory cell to a third voltage higher than used for said programoperation, then f) lowering said drain diffusion voltage to a valuebelow said drain and source equalize voltage, then g) comparing saidsource diffusion voltage to a reference voltage.
 9. The method of claim8, wherein lowering said drain diffusion voltage is done to a firstpredetermined value that allows said source diffusion voltage to remainunchanged when a threshold voltage of said selected storage site isabove a second predetermined value.
 10. The method of claim 8, whereinlowering of said drain diffusion voltage is done to a firstpredetermined value that allows said source diffusion voltage to fallslowly when a threshold voltage of said selected storage site is above asecond predetermined value.
 11. The method of claim 8, wherein floatingsaid drain and source diffusions allows a transfer of charge betweensaid drain and source diffusions until an equilibrium is reached. 12.The method of claim 8, wherein equalization of source and drain is donewith a separate equalization transistor.
 13. The method of claim 8,wherein equalization of source and drain occurs when word line is raisedto said third high voltage.
 14. The method of claim 8, whereinequalizing said drain and said source diffusion voltages results in anequalized voltage that is approximately half of said drain diffusionvoltage during said program operation.
 15. The method of claim 8,wherein comparing said source voltage to said reference voltage is donewith a sense amplifier and determines said selected storage site isprogrammed when said source voltage does not fall below said referencevoltage within fixed time interval.
 16. The method of claim 8, whereincomparing said source diffusion voltage to said reference voltage is areverse read operation using a sense amplifier.
 17. A method to programverify a dual storage site MONOS memory site using a forward readoperation, comprising: a) Maintaining a first voltage coupled to a firstcontrol gate located above an unselected storage site of a MONOS memorycell to be same as for a program operation, b) Lowering a second voltagecoupled to a second control gate above a selected storage site of saidmemory cell to a value less than that used for said program operation,c) disconnecting and floating a drain diffusion and a source diffusionof said memory cell, then d) equalizing said drain diffusion voltage andsaid source diffusion voltage of said memory cell, e) biasing a wordgate voltage of said memory cell to a third voltage higher than thatused for said program operation, then f) lowering said source diffusionvoltage to a value below said drain and source equalize voltage, then g)comparing said drain diffusion voltage to a reference voltage.
 18. Themethod of claim 17, wherein lowering said source diffusion voltage isdone to a first predetermined value that allows said drain diffusionvoltage to remain unchanged when a threshold voltage of said selectedstorage site is above a second predetermined value.
 19. The method ofclaim 17, wherein floating said drain and source diffusions allows atransfer of charge between said drain and said source until anequilibrium is reached.
 20. The method of claim 17, wherein equalizationof source and drain voltages is done with a separate equalizationtransistor.
 21. The method of claim 17, wherein equalization of sourceand drain voltages occurs when word line is raised to said third highvoltage.
 22. The method of claim 17, wherein equalizing said drain andsource diffusion voltages results in an equalized voltage that isapproximately half of said drain diffusion voltage during said programoperation.
 23. The method of claim 17, wherein comparing said drainvoltage to said reference voltage is done with a sense amplifier anddetermines said selected storage site is programmed when said drainvoltage does not fall below said reference voltage within a fixed timeinterval.
 24. The method of claim 17, wherein comparing said draindiffusion voltage to said reference voltage is a forward read operationusing a sense amplifier.
 25. A method of programming a dual storage siteMONOS memory cell using bit line capacitance to provide charge duringCHE programming, comprising: a) biasing a first control gate locatedabove an unselected storage site of a MONOS memory cell to a first highvoltage, b) biasing a second control gate located above a selectedstorage site of said memory cell to a second high voltage, c) biasing afirst diffusion below said first control gate to zero volts, d) basing asecond diffusion below said second control gate to a third high voltage,e) biasing a word gate of said memory cell to zero volts, then f)floating said first and second control gates and said first and seconddiffusions, then g) increasing said word gate voltage to a predeterminedvalue, then h) programming said selected storage site with a flow ofelectrons between said first and second diffusions.
 26. The method ofclaim 25, wherein biasing said second diffusion provides a charge on abit line coupled to said second diffusion that produces said flow ofelectrons between said first and second diffusions when said word gatevoltage is increased.
 27. The method of claim 26, wherein said flow ofelectrons between said first and second diffusions programs saidselected storage site with CHE injection.
 28. The method of claim 27,wherein said word gate voltage limits the extent of equalization betweenfirst and second diffusions and prevents said flow of electrons when thefirst diffusion reaches a voltage equal to said word gate voltage minusa threshold voltage of said word gate.
 29. The method of claim 25,wherein said first diffusion is a source and said second diffusion is adrain.
 30. A method to program verify of a dual storage site MONOSmemory cell using capacitance coupling of control gate lines,comprising: a) programming a selected storage site of a dual storagesite MONOS memory cell using bit line capacitance to provide chargeduring a CHE program operation thereafter a first control gate is leftfloating with a first charged voltage, a second control gate is leftfloating with a second charged voltage, a first diffusion is leftfloating with a third charged voltage and a second diffusion is leftfloating with a fourth charged voltage, b) increasing a word gatevoltage of said memory cell from a program voltage level to a highvoltage, then c) equalizing said third and fourth charged voltages, thend) biasing said second diffusion to a voltage below said equalized thirdand fourth charged voltages, then e) measuring said first diffusionvoltage with a sense amplifier to determine whether said selectedstorage site is programmed.
 31. The method of claim 30, wherein biasingsaid second diffusion to a voltage below said equalized third and fourthcharged voltages to a value to produce little or change in said firstdiffusion voltage when said storage site is programmed
 32. The method ofclaim 30, wherein said control lines of said first and second controlgates are capacitive coupled whereby said first charged voltageincreases and said second charged voltage decreases when said word gatevoltage is increased to said high voltage.
 33. The method of claim 32,wherein said biased second diffusion voltage subtracted from saiddecreased second charged voltage equals a target threshold voltage. 34.The method of claim 32, where in target threshold voltage may be lessthan said second diffusion voltage subtracted from said second chargedvoltage in order to reduce program verify time.
 35. The method of claim30, wherein said first diffusion is a source and said second diffusionis a drain of said memory cell.
 36. A programming means for a dualstorage site MONOS memory cell, comprising: a) a means for biasing aword gate to limit memory cell current, b) a means for biasing a firstcontrol gate to override threshold voltage of an unselected storage sitebeneath said first control gate, c) a means for coupling a sourcediffusion to a load device, d) a means for biasing a second control gateto inject electrons into a selected storage site beneath said secondcontrol gate, e) a means for suppressing a disturb condition in anunselected diffusion of an adjacent cell.
 37. The programming means ofclaim 36, wherein the means for biasing said word gate to limit memorycurrent uses a low voltage to control cell current to a fewmicroamperes.
 38. The programming means of claim 36, wherein said meansfor coupling said source diffusion to a load device limits current flow.39. The programming means of claim 36, wherein said means forsuppressing said disturb condition in the unselected diffusion of theadjacent cell increases a voltage coupled to said unselected diffusion.40. A program verification means for a dual storage site MONOS memorycell, comprising: a) a means for switching to a program verify operationfrom a program operation, b) a means for disconnecting bias and floatinga drain and a source diffusion of a cell being programmed, c) a meansfor biasing a word gate to a high voltage, d) a means for measuring asource voltage to be compared to a reference voltage.
 41. The programverification means of claim 40, wherein the means for switching to aprogram verify operation entails selecting voltages that minimizecharging and discharging of bit lines and control lines to improveperformance.
 42. The program verification means of claim 40, wherein themeans for disconnecting bias and floating said drain and sourcediffusions allows a transfer of charge between said drain and saidsource until an equilibrium exists.
 43. The program verification meansof claim 40, wherein said means for measuring is done using a drainvoltage.
 44. A minimum conversion time means between program and programverify operations, comprising: a) a means for setting bias voltages tobe same or similar between program and program verify operations, b) ameans for reading a programmed voltage of a cell using a forward orreverse read direction.
 45. The minimum conversion time means of claim44, wherein the means for setting bias voltages to be the same orsimilar between program and program verify operations comprises a bitdiffusion voltage, a first control gate voltage and a second controlgate voltage.
 46. The minimum conversion time means of claim 44, whereinthe means for reading a programmed voltage of a cell using a forwardread direction couples a low voltage to a diffusion opposite to aselected nitrite storage site being programmed.
 47. The minimumconversion time means of claim 44, wherein the means for reading aprogrammed voltage of a cell using a reverse read direction couples alow voltage to a diffusion next to a selected nitrite storage site beingprogrammed.